1. Field of the Invention
The present invention relates to a level shifter, and more particularly to a level shifter that can receive and convert signals with various voltage level types to signals with a normalized voltage level.
2. Description of the Prior Art
A level shifter is a circuit that converts an input signal from one voltage logic level to another voltage logic level. For example, the shifter can convert a CMOS logic level signal into a TTL logic level signal and vice versa. A conventional level shifter is typically able to convert a signal of a certain logic level type to a signal of another logic level type. However, a conventional level shifter is not able to convert a signal that may have one of many different logic level types to a signal of another logic level type.
Level shifters are often used to interface between a semiconductor memory device and devices external to the memory device. In other words, the conventional semiconductor memory device is equipped with a level shifter in case the logic levels of externally input signals are different from the voltage levels of internal logic levels within the memory device. The level shifter converts the voltage logic levels of external signals into signals having the internal logical voltage levels. These kinds of level shifters typically consist of sense amplifiers that are connected to each signal input terminal of the memory device and convert the voltage logic levels of the externally input data signals, address signals, control signals and clock signals into internal voltage logic levels.
When the level of the external signal is fixed at one level, the voltage logic levels of these signals can be correctly amplified and outputted. But when the voltage logic levels of the external signal can vary among several voltage logic level types, then the voltage logic levels of these signals cannot be correctly amplified and outputted. This is due to the fact that an amplifier is typically designed to amplify voltage logic levels of one particular logic type. The conventional semiconductor memory device, therefore, can only amplify and convert the levels of external signals to the internal voltage levels when the voltage logic levels of the external signals are of one particular logic type.
In order for the conventional semiconductor memory device to amplify input signals of multiple voltage logic level types and convert them to internal voltage logic levels, the device is equipped with a sense amplifier designed to produce signals of the correct internal voltage levels in response to external signals that can have multiple voltage logic levels. Such a sense amp is typically equipped with a switch for selecting one of several sense amplifiers to operate according to the voltage logic levels of the external signal. The structure of the resulting circuit can be quite complex.
For example, a level shifter for the clock signal generating circuit of a conventional synchronous type semiconductor device will receive an external clock signal or inverted clock signal. The level shifter will amplify the voltage logic levels of the clock signal in order to generate clock signal levels having the appropriate internal high and low logic levels. The level shifter amplifies the voltages of the high and low levels of the clock signal and outputs the resulting amplified signal to the clock signal generating circuit. The clock signal generating circuit will then generate an internal clock signal in response to the signal output by the level shifter.
However, if the levels of the external clock signal vary among multiple voltage logic levels, then it is difficult for the sense amplifier to operate and convert the various voltage levels of the external clock signals.
In other words, a sense amplifier of a level shifter can be designed to generate the appropriate internal logic levels from a clock signal having a LVTTL (low voltage transistor--transistor logic) level, where a low logic level is 0V and a high logic level is 3.3V. Problems arise, however, because the sense amplifier cannot also correctly generate the appropriate internal logic levels from a clock signal changing having a HSTL (high speed transistor logic) level, where a low logic level is 0V and a high logic level is 1.5V. However, when additional sense amplifiers are included in the design in order to correctly shift multiple voltage levels for the input clock signal, then the circuit becomes quite complicated.
Below is an explanation of a conventional level shifter and the semiconductor memory device used with it.
FIG. 1 illustrates a conventional level shifter circuit. The level shifter shown in FIG. 1 includes a PMOS transistor P2 having a source coupled to a source voltage VDD. PMOS transistor P1 has a source connected to the drain of PMOS transistor P2 and a gate that receives an inverted signal XDIB. PMOS transistor P3 has a drain connected to the output terminal DO, a gate that receives a signal XDI, and a source connected to the drain of the PMOS transistor P2. NMOS transistor N1 has a source connected to a ground voltage terminal, and gate and drain terminals that are both connected to the drain of PMOS transistor P1 and the gate of PMOS transistor P2. NMOS transistor N2 has a source connected to the ground voltage tenninal, a gate connected to the gate of PMOS transistor P2 and the gate of NMOS transistor N1, and a drain connected to the drain of PMOS transistor P3.
The structure of the level shifter shown in FIG. 1 is that of a sense amplifier. When signal XDI and inverted signal XDIB are 0V and 3.3V, respectively, and the source voltage VDD is 3.3V, then PMOS transistor P3 becomes turned on more than PMOS transistor P1 and the output voltage at terminal DO becomes 3.3V. Conversely, when signal XDI and inverted signal XDIB are 3.3V and 0V, respectively, and the source voltage VDD is 3.3V, then PMOS transistor P1 becomes more turned on than PMOS transistor P3 and the output signal at terminal DO becomes 0V. In other words, the level shifter shown in FIG. 1 can, when the voltage logic level of the input signal is 3.3V, amplify the difference and correctly generate the appropriate signal levels at output terminal DO of 0V and 3.3V. But if the voltage logic levels of the signal being inputted is either larger or smaller than these voltage levels, then the level shifter cannot correctly amplify and generate the appropriate voltage logic levels in the output signal at DO.
FIG. 2 shows a block diagram of a semiconductor memory device that uses the level shifter shown in FIG. 1. The memory device includes an address input buffer 10, a data input buffer 12, a control signal input buffer 14, a clock signal input buffer 16, a control signal generating circuit 18, a pulse generating circuit 20, a memory cell array 22, a row address decoder 24, a write driver 26, a column address decoder 28, a sense amplifier 30, and a data output buffer 32.
In the circuit shown in FIG. 2, the address input buffer 10, the data input buffer 12, the control signal input buffer 14, and the clock signal input buffer 16 are constructed using level shifters. In other words, address input buffer 10 is composed of a x level shifters, data input buffer 12 is composed of y level shifters, control signal input buffer 14 is composed of k level shifters, and data output buffer 32 is composed of z level shifters.
The address input buffer 10 outputs x address signals by buffering each of the input signals XAx. In other words, the address input buffer converts the voltage logic levels of external signals XAx to internal voltage logic levels and outputs them. The data input buffer 12, the control signal input buffer 14 and the clock signal input buffer 16 buffer and output data input signals XDy, control signals XCk, and clock signal XCK, respectively.
As for the clock signal input buffer 16, when the clock signal or a inverted clock signal is externally input, the appropriate clock signal can be directly inputted and buffered without the generation of a inverted clock signal by internally inverting the clock signal. Pulse generating circuit 20 then generates an internal clock signal ICK having the appropriate internal voltage level from the buffered clock signal received from clock signal input buffer 16.
The control signal generating circuit 18 generates an internal control signal IC by buffering the external control signal XCk received by control signal input buffer 14. The control signal IC is used to control write driver 26, sense amplifier 30, and data output buffer 32 during write or read operations.
Memory cell array 22 is composed of cells that store data transmitted from a bit line pair within the array during a write operation. During a read operation, the data stored in the cells is transmitted to the bit line pair. The row address decoder 24 decodes the line addresses buffered by the address input buffer 10 and generates word line selection signals WL1, WL2, . . . , WLn.
The write driver 26, during a write operation, transmits the data buffered by data input buffer 12 onto the data line pair DL and DLB which are connected to bit line pairs of memory cell array 22. The data line pair DL and DLB are also connected to sense amplifier 30 that receives and amplifies the data transmitted to the data line pair during a read operation. The sense amplifier outputs the amplified data received from the memory cell array to output buffer 32. Output buffer 32 buffers the data received from sense amplifier 30 and outputs the data from the memory device via z external output data lines XDOz.
As shown in FIG. 2, the conventional semiconductor memory device utilizes a level shifter structure composed of a sense amplifier in order to construct input and output buffers.
Thus, the memory device can only convert between internal voltage logic levels and the voltage logic levels of external signals having a single logic level type.
For example, if the low logic level of the externally input signal is 0V and the high logic level is 1.5V while the internal low logic level of the source voltage is 0V and the internal high logic level is 3.3V, then the voltage levels of the external signals can be amplified and outputted as the internal voltage levels. However, if the external low logic level is 0V and the external high logic level is 1.5V, while the internal low logic level is 0V and the internal high logic level is 2.5V, then the voltage levels of the external signals cannot be correctly amplified and converted to the internal voltage levels.
Therefore, if the voltage levels of the external signals change, then the sense amplifiers within the level shifters of conventional semiconductor memory devices cannot correctly amplify and convert between the external voltage logic levels and the internal voltage logic levels.